This project uses classes that model the memory blocks that can easily implemented on chips for embedded systems.

The challenge is to define the classes and memory contents such that C code can be executed in the fewest clock intervals when converted to hardware.  This leads to  need for the classes that represent state machines to hace a clock method that controls the state changes and for a scheme to make it appear that all state machines operate in parallel.

They are still snickering over at the CoffeeHouse where I started a thread "A New Architecture for Embedded Processors".

So here is what I have working so far.  Included in the zip is a text cEx1 that is simple C code that should be opened when the app shows the open file box.  the first step generates the ram loads and then asks whether to run the sim step.  That produces a wave form showing some of the state changes.  Clicking on the Cycle by cycle button shows a list box where the C sequence is shown.

There is still work to do with testing and function additions pending.  My claim is that any available processor woul take many more cycles to execute the sequence.

All variables are treated as uint types and function calls have to be added.