Minh wrote:How does DMA fit in all this? Or is that something outside of this lib?
tsilb wrote:Interesting video, but it raises some questions: How does the cache manager (Cacheman?) interact with the multiple memory controllers commensurate with multi procs or multi cores? Seems the video was about to address that but kinda skipped over it like a sensitive topic or something. How does the cache manager keep track of which memory controller owns what addresses? Does it multiply the amount of buffer space or divide the existing buffer space by the number of processors?
It was said that the cache manager's lazy writers may take ~8 seconds to flush dirty pages to disk. What measures, if any, are in place to protect unflushed cached data during power outages or hardware failures?
Excellent videos. Nice to see a low level technical one once in a while. I happen to be optimizing some code that handles multi-hundred meg and sometimes gigabyte files so seeing how things work under the hood has been very interesting and helpful.
codan wrote:It was said that the cache manager's lazy writers may take ~8 seconds to flush dirty pages to disk. What measures, if any, are in place to protect unflushed cached data during power outages or hardware failures?
Memory Manager will be covered in the not too distant future in this series. Keep in mind that these videos serve as introductions to the technology and the people behind it. Books are generally really good for highly specific and detailed analysis of complex topics. Video, on the other hand, really isn't. So, Going Deep will only be able to go so far and still keep you wanting to watch!C