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View Thread: Roslyn and FPGA/ASIC design
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    Here is the link to the excellent video that relates to the underlying problem with FPGA design tools.

    The HDL tools used for design correspond to the "back end" of a real compiler.

    Microsoft designers (project Catapult, etc.) have commented on the pain involved in using the existing tools.

    That is because it is like trying to write an application in byte code.

    Design boils down to moving data through Boolean networks(ALUS, etc. for computation and using conditional expressions

    to control the path and sequences.

    Basically a computer does computation by combining two operands in the ALU.  An FPGA may have many ALUs

    working in parallel and that is the key to the performance.  However, data dependencies affect the sequencing

    as well the algorithms.

    The algorithm sequences/conditions (if, else, for, etc.) are all provided by the Roslyn API.  If the algorithm has

    only sequencing conditions, then the ALUS can work in parallel.

    In short, The Roslyn API(and the debug/edit) is the ultimate "front end" for BOTH program development and

    hardware design. 

    Roslyn needs to be able to emit HDL as well as byte code.  And leave the data dependencies up to the designer.

    FPGA accelerators and GPUs depend upon no data dependencies -- send out a block of raw data and receive a block of

    processed data.