Characterization of OLTP Workloads: from Micro-architecture to Power/Performance

Play Characterization of OLTP Workloads: from Micro-architecture to Power/Performance
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Traditional online transaction processing (OLTP) systems severely under-utilize the micro-architectural resources; more than half of the CPU cycles go to stalls, and the number of instructions retired per cycle barely reaches one on machines that are able to retire up to four. This causes large power waste, and renders the power-hungry, heavily optimized Intel Xeon processors energy-inefficient. In this talk, we firstly compare the traditional and main-memory OLTP systems in terms of their micro-architectural behavior on an Intel Xeon processor. We then proceed by comparing the high-end Intel Xeon processor with a recently announced server-grade ARM processor in terms of their power, throughput and latency characteristics when running OLTP workloads. Based on our observations, we lastly comment on power-saving and performance opportunities in co-designing OLTP software and hardware.

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